`timescale 1ns / 1ps
/*
 Copyright 2020 Sean Xiao, jxzsxsp@qq.com
 
 Licensed under the Apache License, Version 2.0 (the "License");
 you may not use this file except in compliance with the License.
 You may obtain a copy of the License at
 
 http://www.apache.org/licenses/LICENSE-2.0
 
 Unless required by applicable law or agreed to in writing, software
 distributed under the License is distributed on an "AS IS" BASIS,
 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 See the License for the specific language governing permissions and
 limitations under the License.
 */

module dug_csr(
    input sys_clk,
    
    input [ 11: 0 ] i_csr_addr,
    //input           i_csr_val,
    input i_csr_wen,
    
    output reg o_wr_dcsr_ena,
    output reg o_wr_dpc_ena,
    output reg o_wr_dscrh_ena,

    input rst_n
);

always@( * )   //csr read
case ( i_csr_addr & {12{i_csr_wen}} )
    12'h7b0: o_wr_dcsr_ena <= 1'b1;
    12'h7b1: o_wr_dpc_ena <= 1'b1;
    12'h7b2: o_wr_dscrh_ena <= 1'b1;
    default:
    begin
        o_wr_dcsr_ena <= 1'b0;
        o_wr_dpc_ena <= 1'b0;
        o_wr_dscrh_ena <= 1'b0;
    end

endcase

endmodule
